The present invention disclosed herein relates to semiconductor devices, and more particularly, to flash memory devices and related fabrication methods.
A flash memory device is one type of nonvolatile memory device that may be capable of retaining stored data regardless of the presence of power supply, and may be configured to electrically change the stored data more easily than other nonvolatile memory devices, such as a read only memory (ROM) devices.
The flash memory device may be classified into two types according to the kind of a structure for storing charges, of which one is a floating gate type flash memory and the other one is a charge trap type flash memory. In more detail, the floating gate flash memory, may store the charges in a floating gate electrode disposed under a control gate electrode. However, since the conductive floating gate electrode should be electrically isolated for data retention, the manufacturing process for the floating gate type flash memory may be more complicated in comparison with that of the charge trap type flash memory. In addition, a gate structure of the floating gate type flash memory may have a relatively high aspect ratio, which may result in technical difficulties in follow-up processes.
In contrast, because the charge trap type flash memory may use a gate insulating layer formed of a material having sufficient trap sites therein, e.g., silicon nitride, it may have a similar structure to a conventional metal oxide semiconductor field effect transistor (MOSFET). Accordingly, the manufacturing process for the charge trap type flash memory may be simpler and easy in comparison with the floating gate type flash memory. For this reason, various research has been performed regarding the commercial feasibility of the charge type trap type flash memory.
Meanwhile, the flash memory device may be classified into a NOR type structure or a NAND type structure based on how memory cells are connected to a bit line and a source line. In detail, the NOR type flash memory device (hereinafter referred to as a NOR flash) may be configured such that respective memory cells are connected to the bit line and the source line in parallel, and thus may have relatively speedy random access. Therefore, the NOR flash may be mainly used in basic input output systems (BIOS), cellular phones, personal digital assistants (PDA), and so forth.
In contrast, the NAND type flash memory device (hereinafter referred to as a NAND flash) may be configured such that memory cells are connected to a bit line BL0-n and a common source line CSL in series (see FIG. 1). As shown in FIG. 1, a cell array of the NAND flash includes a plurality of cell strings 5, and each of the cell strings 5 has a plurality of memory cells connected to each other in series. Herein, respective gate electrodes of the memory cells are connected to respective different word lines WL0˜WLm. Furthermore, ground selection transistors (connected to each other by a ground selection line GSL) and string selection transistors (connected to each other by a string selection line SSL) are disposed at both ends of the cell strings 5, so as to control electrical connection between the memory cells and the bit line BL0˜BLn/the common source line CSL.
Due to the serial connection structure of the NAND flash, the NAND flash may have a high degree of integration among existing semiconductor devices. In addition, since the NAND flash may adopt an operation scheme that simultaneously changes data stored in the plurality of memory cells, the update speed of data may be faster than the NOR flash. Because of high integration and rapid update speed, the NAND flash may be mainly used in portable electronic devices requiring a mass storage device such as digital cameras, MP3 players, or the like. The IDC, a market research firm, forecasts that the market of the NAND flash product will be expanded more and more due to increasing demand for portable electronic devices.
FIG. 2 is a cross-sectional view illustrating a portion of a cell array of a conventional charge trap type NAND flash memory device.
Referring to FIG. 2, gates 30 crossing over active regions are disposed on a semiconductor substrate 10, and impurity regions 70 are disposed on the active region between the gates 30. The gates 30 are used as the word lines WL0˜WLn, the string selection lines SSL, and the ground selection lines GSL. The impurity region 70S disposed at one side of the ground selection line GSL is connected to a common source line CSL through a first plug 51, and the impurity region 70D disposed at one side of the string selection line SSL is connected to a bit line BL through a second plug 52.
In addition, halo regions 80 and 82 are formed around the lower portion of the impurity region 70. The halo regions 80 and 82 may be formed through an ion implantation process using the gates 30 as masks. However, according to the conventional charge trap type flash memory, a space D2 between the ground selection line GSL and the word line WL0 adjacent thereto and a space D2 between the string selection line SSL and the word line WLm adjacent thereto are greater than a space D1 between two adjacent word lines, e.g., between the word lines WL0 and WL1. This space difference may cause the amount of impurity ions implanted onto the active region to be different. In addition, this problem may become more serious in a tilt ion implantation process. Therefore, the halo region 80 at one side of the outermost word line WL0 and WLm may have a different impurity concentration than the halo region 82 at the other side thereof.
The difference in the impurity concentrations may cause the operational characteristics (particularly, the difference in the threshold voltage distribution of an erased cell) of the outermost word lines WL0 and WLm to be different from the operational characteristics of the inner word lines WL1˜-WLm-1, as illustrated in FIG. 3. Also, the same problems in the operational characteristic differences between the outermost word lines and the inner word lines may occur in the floating gate type NAND flash memory.